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25 #ifndef _AROARFW_I2C_H_
26 #define _AROARFW_I2C_H_
32 #define I2C_OFFSET_IFVERSION 0x00
33 #define I2C_OFFSET_STATUS0 0x01
35 #define I2C_OFFSET_BANKSELECT 0x02
37 #define I2C_OFFSET_DEVERROR 0x03
39 #define I2C_OFFSET_BANKDATA 0x04
43 #define RI2C_INTERFACE_VERSION 0x00
46 #define RI2C_STATUS0_NONE 0x00
47 #define RI2C_STATUS0_DEVICE_READY 0x01
49 #define RI2C_STATUS0_SELFCHECK_PASSED 0x02
51 #define RI2C_STATUS0_SELFCHECK_ERROR 0x04
53 #define RI2C_STATUS0_UPDATES_PENDING 0x08
57 #define RI2C_STATUS1_NONE 0x00
58 #define RI2C_STATUS2_NONE 0x00
62 #define RI2C_CAPS0_BRIDGE_NONE 0x00
63 #define RI2C_CAPS0_BRIDGE_NETWORK 0x01
65 #define RI2C_CAPS0_BRIDGE_ETHERNET 0x02
67 #define RI2C_CAPS0_BRIDGE_I2C 0x04
69 #define RI2C_CAPS0_BRIDGE_SPI 0x08
71 #define RI2C_CAPS0_BRIDGE_DMX512 0x10
73 #define RI2C_CAPS0_BRIDGE_MIDI 0x20
75 #define RI2C_CAPS0_BRIDGE_WAVEFORM 0x40
77 #define RI2C_CAPS0_BRIDGE_RESERVED7 0x80